1. Field of the Invention
This invention relates to decoder systems and to methods of manufacture of such systems.
The decoder system may be used with an electrode arrangement for an array of electrically-controllable elements, comprising a series of generally parallel electrodes each for extending along a respective line of the electrically-controllable elements, and a series of driver lines for receiving driving signals and supplying them to the electrodes. An electrically-controllable array device may be provided, comprising: first and second such electrode arrangements having their electrodes crossing each other, and an array of electrically-controllable elements each disposed at a crossing of a respective one of the electrodes of the first arrangement and a respective one of the electrodes of the second arrangement. The electrically-controllable elements may, for example, be provided by respective portions of a layer of material sandwiched between the electrodes of the first and second electrode arrangements. The electrically-controllable elements may have a plurality of stable states, and they may be formed by, for example, a bistable ferroelectric liquid crystal material, with the device forming a liquid crystal display panel.
2. Description of Related Art
Such an electrode arrangement is well known, and a conventional ferroelectric liquid crystal display panel having a pair of such electrode arrangements is illustrated in FIG. 1. The display panel 10 comprises lower and upper sheets of glass 12, 14, which sandwich between them a layer of ferroelectric liquid crystal material. At least one of the sheets 12, 14 acts as a plane polarising filter, or has a polarising layer applied to it. The upper surface of the lower sheet 12 is formed with a series of elongate row electrodes 16 oriented in the left-right direction, and the lower surface of the upper sheet 14 is formed with a series of elongate column electrodes 18 oriented in the up-down direction. The electrodes are transparent and formed of, for example, indium-tin-oxide (ITO). The surfaces in contact with the liquid crystal material are treated so as to align the molecules of the liquid crystal material. The portion of the liquid crystal material at each crossing point of a row electrode 16 and a column electrode 18 provides a respective pixel of the display. The ferroelectric liquid crystal material is such that, at each crossing point, if a potential difference having a value greater than a threshold level VT+ is applied for a sufficient time between the electrodes 16, 18 at that crossing point, the material will change to a first state, if it is not already in that state, and if an electric field having a value in excess of a threshold level VTxe2x88x92, of opposite polarity, is applied for a sufficient time between the electrodes 16, 18, the material will change to a second state, if it is not already in that state. The polarising effect of the crystal on light is different in the first and second states, and in combination with the polarising effect of the sheet(s) 12, 14, causes the pixel to appear black in one of the states and transparent (hereinafter called xe2x80x9cwhitexe2x80x9d) in the other state.
The row electrodes 16 are each connected to a respective output of a row driver 20, and the column electrodes 18 are each connected to a respective output of a column driver 22. The row and column drivers 20, 22 are controlled by a controller 24, such as a microprocessor. The row and column drivers 20, 22 are each operable to apply voltages to the respective electrodes 16, 18 to cause the pixels to switch to required states so as to form an image on the display panel 10 and to change the image as required. Various driving schemes are known in the art. For example, in one scheme, a voltage VC1 is applied by the column driver 22 to all of the column electrodes 18, and a voltage VR1 is sequentially applied by the row driver 20 to each of the row electrodes 16, where VC1xe2x88x92VR1 less than VTxe2x88x92, so as to clear the display 10 row-by-row to white. Then, a voltage VR2 is sequentially applied by the row driver 20 to the row electrodes 16, and whilst that voltage is being applied to a particular row electrode, a voltage VC2 is applied by the column driver 20 to one or more selected column electrodes 18, where VC2xe2x88x92VR2 greater than VT+, so as to write black to the pixels at the intersections of that row electrode 16 and the or each selected column electrode 18. In another scheme, rather than clearing the whole display to white and then writing selected pixels to black, the rows are addressed sequentially and all of the pixels in the selected row are cleared to white and immediately afterwards selected pixels in that row are written to black. In a modification to this scheme, rather than addressing the rows sequentially, they are addressed as and when required. In another modification, rather than clearing a whole row of pixels to white and then writing selected pixels to black, pixels which are to be changed from black to white are written to white, and pixels which are to be changed from white to black are written to black.
There is a desire to manufacture such liquid crystal display panels with ever increasing sizes and ever increasing resolutions (decreasing row and column electrodes pitches). In the arrangement shown in FIG. 1, the row and column drivers 20, 22 are fabricated in silicon, and there is a problem in providing proper interconnections between the drivers 20, 22 and the electrodes 16, 18 on the glass sheets 12, 14. It will be appreciated that with increasing sizes and increasing resolutions, the interconnection problem also increases, because the interconnections are greater in number and more closely spaced.
To tackle this problem, each electrode may be connected to a plurality of the driver lines each via a respective impedance, such as a resistor. Such an arrangement is known from patent document U.S. Pat. No. 5,034,736 which describes a driving scheme which is illustrated in FIG. 2 of the accompanying drawings and which will now be briefly described.
In FIG. 2, there are two row drivers 20L, 20R, each of which has three outputs 1, 2, 3 and 4, 5, 6. Output 1 of the left row driver 20L is connected by respective resistors 26 to the left hand ends of row electrodes 16 numbered 1, 4, 7. Output 2 of the left row driver 20L is connected by respective resistors 26 to the left hand ends of row electrodes 2, 5, 8. Output 3 of the left row driver 20L is connected by respective resistors 26 to the left hand ends of row electrodes 3, 6, 9. Output 4 of the right row driver 20R is connected by respective resistors 26 to the right hand ends of row electrodes 1, 5, 9. Output 5 of the right row driver 20R is connected by respective resistors 26 to the right hand ends of row electrodes 2, 6, 7. Output 6 of the right row driver 20R is connected by respective resistors 26 to the right hand ends of row electrodes 3, 4, 8. Furthermore, there are two column drivers 22T, 22B, each of which has three outputs 1, 2, 3 and 4, 5, 6. The top column driver 22T is connected to the upper ends of the column electrodes 18 by respective resistors 26 in a similar fashion to the connection of the left row driver 20L to the left hand ends of the row electrodes 16. Also, the bottom column driver 22B is connected to the lower ends of the column electrodes 18 by respective resistors 26 in a similar fashion to the connection of the right row driver 20R to the right hand ends of the row electrodes 16.
In the example given in U.S. Pat. No. 5,034,736, all of the resistors 26 are of the same value, the drivers 20L, 20R, 22T, 22B can set their output voltages at particular levels, and the liquid crystal material has particular particular positive and negative threshold voltages VTxe2x88x92, VT+. It will therefore be appreciated that if the voltages applied to the resistors 26 at the opposite ends of a particular electrode 16, 18 are equal, the voltage of that electrode will be the same as the applied voltage. However, if the voltages applied to the resistors 26 of a particular electrode 16, 18 differ, the voltage of that electrode will be the average of the applied voltages. It is therefore possible to drive the electrodes so that a voltage exceeding the threshold voltages VTxe2x88x92, VT+ can be applied across any selected intersection of the row and column electrodes in order to change the state of the liquid crystal material at that intersection, without applying a voltage in excess of the threshold voltages VTxe2x88x92, VT+ at any other intersection. The advantage which is provided is that the required total number of outputs from the drivers 22L, 20R, 22T, 22B, and therefore the total number of interconnections between the drivers 22L, 20R, 22T, 22B and the display panel 10, has been reduced from eighteen (in the case of FIG. 1) to twelve (in the case of FIG. 2.)
U.S. Pat. No. 5,034,736 teaches that the arrangement shown in FIG. 2 represents the maximum number of column electrodes and the maximum number of row electrodes which can be activated by the drivers (with the given number of outputs). The prior specification also teaches that the connections permit the drivers to handle a number of electrodes equal to the square of the number of outputs of a driver (that is, nine electrodes for three outputs), which is a much larger number of electrodes than can be handled by drivers in circuitry of the prior art of FIG. 1 where one driver port is assigned to only one electrode. It should be noted, of course, that taking into account the outputs of the driver at the other end of the electrodes, the relationship between the maximum number N of electrodes and the number n of driver outputs for those electrodes envisaged by U.S. Pat. No. 5,034,736 is N=n2/4, rather than N=n2.
Although at first sight the teaching of the prior art might appear to be correct, it is in fact incorrect and places unnecessary restrictions on the interconnect reduction.
The decoder system of the present invention may, for example, be used with an improved electrode arrangement in which the driver lines are so connected to the electrodes such that the driver lines cannot be split into a pair of arbitrary groups of the driver lines for which (a) each group has generally the same number of driver lines and (b) each electrode is so connected to at least one of the driver lines in one of the groups and to at least one of the driver lines in the other of the groups.
Alternatively stated, in such an electrode arrangement the driver lines are so connected to the electrodes such that there is at least one closed circuit from one of the driver line s via at least some of the impedances and at least some of the other driver lines back to said one driver line, the closed circuit including the impedances for an odd number of the electrodes.
For example, in a simple example which provides the same degree of discrimination between setting and not setting the state of a pixel, or memory element, as the prior art of U.S. Pat. No. 5,034,736, this improved electrode arrangement enables the relationship between the maximum number N of electrodes and the number n of driver outputs for those electrodes to be N=nxc2x7(nxe2x88x921)/2, rather than N=n2/4, and is therefore larger for all but the trivial cases of n=1 and n=2. Thus, the row electrodes 16 of the display panel of FIG. 2 can be driven by five driver outputs, rather than six. Whilst this 16⅔% reduction in the required driver outputs in the case of N=9 may seem small, it is significant. For larger values of N, the improvement becomes more marked. In a practical application where the desired height of a monochrome display might be, say, 210 mm and the resolution might be 300 dpi (electrode pitch of 85 xcexcm), the required number of row electrodes would be N=2480. Applying the teaching of U.S. Pat. No. 5,034,736, the required number of row driver outputs is n=100, whereas with the improved electrode arrangement, the required number of row driver outputs is n=71, that is a 29% reduction. (It can be shown that, in the case where the number N of row electrodes is very large, the maximum reduction, employing only this advance over the prior art, is 100xe2x88x92502%, that is about 29.29%.)
U.S. Pat. No. 5,034,736 also teaches that it is essential that the electrodes each have two terminals, a xe2x80x9cfront terminalxe2x80x9d and a xe2x80x9cback terminalxe2x80x9d, to which the respective two resistors are connected, and in all of the examples given in U.S. Pat. No. 5,034,736 these two terminals are at opposite ends of the respective electrode.
In the improved electrode arrangement described herein, each electrode may be connected to at least three of the driver lines, for example three, four, five, six, seven, eight or more of the driver lines.
With this feature, which recognises that the connections to each electrode do not need to be (but can be) made separately and at its two ends, the ratio of the number N of electrodes to the number n of driver lines can be increased considerably. For example, if FIG. 2 is modified so that each row electrode is connected to a different three of the six driver outputs, the number of electrodes can be increased from N=9 to N=20. More generally, for three connections to each electrode, the number N of electrodes which can be driven is related to the cube of the number n of driver lines by N=nxc2x7(nxe2x88x921)xc2x7(nxe2x88x922)/6, and so the benefits rise rapidly with n, becoming very marked for large values of n and N. For example, to drive 2480 electrodes, as mentioned above, using three connections per electrode requires 26 driver lines, as compared with 100 driver lines for an arrangement following the teaching of U.S. Pat. No. 5,034,736, that is a 74% reduction in driver lines. With a greater number of connections per electrode, the benefits in the increase of the ratio N/n of the number of electrodes to the number of driver lines becomes even more marked, at least for large values of N.
A problem which is introduced by connecting each electrode to a number c of driver lines greater than two is that the discrimination between selecting and not selecting a particular crossing point of the electrodes becomes more marginal. For example, with an addressing scheme having a clear-to-white phase and a selectively-write-to-black phase, if the voltages provided during the write-to-black phase by each driver line for a column electrode are selectably 0V and +VD, and by each driver line for a row electrode are selectably xe2x88x921/4VD and +3/4VD then with the FIG. 2 arrangement (for which c=2), the voltages which can be applied during that phase to a crossing point are 5/4VD, 3/4VD, xe2x88x921/4VD, xe2x88x921/4VD and xe2x88x923/4VD. Assuming that the threshold voltages VT+, VTxe2x88x92 of the liquid crystal are of equal magnitude (VT+=xe2x88x92VTxe2x88x92), then for proper operation they preferably satisfy the relationship 5/4VD greater than VT+ greater than 3/4VD. In other words, there is a tolerance of xc2x11/4VD on the threshold voltages. However, if the number c of driver lines connected to each electrode is increased to c=3, and if the voltages provided during the write-to-black phase by each driver line for a column electrode are selectably 0V and +VD, and by each driver line for a row electrode are selectably xe2x88x921/6VD and +5/6VD, then the voltages which can be applied during the write-to-black phase to a crossing point are 7/6VD, 5/6VD, 1/2VD, 1/6VD, xe2x88x921/6VD, xe2x88x921/2VD and xe2x88x925/6VD. For proper operation, the threshold voltages preferably satisfy the relationship 7/6VD greater than VT+ greater than xc2x75/6VD, which therefore places a tighter tolerance of xc2x11/6VD on the threshold voltages. This ancillary problem is accentuated as the number c of driver lines to which each electrode is connected is increased.
To assist in dealing with this problem, in a preferred form, for any given pair of the electrodes, the number v (if any) of the driver lines to which those electrodes are commonly so connected is at least two less than the number c of the driver lines to which each of those electrodes is so connected. For example, if c is chosen to be four and v is chosen to be two, the arrangement can provide the same degree of xe2x80x9ccrosstalkxe2x80x9d (v/c) as the FIG. 2 arrangement. Although placing this restriction on v causes a reduction in the ratio of N/n, a far greater ratio of N/n can be provided than is envisaged in U.S. Pat. No. 5,034,736. Indeed, it can be shown that for the case where, for example, for c=4 and v=2 (that is v/c=1/2), the improvement is considerable for large values of N, compared with the prior art for which c=2, v=1, and therefore v/c=1/2 also.
For simplicity the electrodes are preferably each so connected to the same number c of the driver lines. Also, for compactness, at least at the positions where the connections for the electrodes are made to the driver lines, the driver lines are preferably oriented generally parallel to each other and generally at right angles to the electrodes and/or the electrodes and the driver lines are preferably disposed on a common substrate.
When the improved electrode arrangement described above is used as one electrode arrangement of a memory and/or display device, the other electrode arrangement may be driven in a conventional manner, or it may also include the improvements.
A first aspect of the invention is concerned with a decoder system which may be used with an electrode arrangement as described above, but which also has other applications. For example, such a decoder system could be used for addressing of arrays of memory elements, or of arrays of sensors such as light sensors, or for mobile communications. More particularly, the first aspect of the invention is concerned with a decoder system comprising: an address input for receiving an address signal representing any of a plurality of address values; a plurality of intermediate nodes (for example the driver lines described above); a decoder responsive to the address signal and arranged to stimulate, for each address value, a respective combination of the intermediate nodes; and a plurality of outputs (for example the connections to the electrodes described above), each responsive to a respective group of the intermediate nodes such that the stimulation applied to that output is dependent upon the stimulation applied by the decoder to each of the intermediate nodes in the respective group.
A decoding system of this type is known from U.S. Pat. No. 5,034,736. In that case, the decoder depends for its operation on a look-up table stored in ROM.
Furthermore, a second aspect of the invention is concerned with a method of manufacturing such a decoder system, comprising the steps of: providing such a decoder which is responsive to an address signal representing any of a plurality of address values and is arranged to stimulate, for each address value, a respective combination of intermediate nodes; providing a plurality of outputs; determining, for each output, a respective group of the intermediate nodes to which that output is to be responsive; and rendering each output responsive to the intermediate nodes in the respective determined group such that the stimulation applied to that output is dependent upon the stimulation applied by the decoder to each of the intermediate nodes in the respective group.
It is difficult in practice to find configurations of connecting the outputs to the intermediate nodes with the necessary properties of a large number N of outputs for a small number n of intermediate nodes, and a small ratio of v/c. Combinatorial searching may be used, but requires careful optimisation, and even then begins to become inefficient in terms of computation time as the number n of intermediate nodes increases, because of the extremely large search space. Fortunately, such lengthy searching is only needed when designing the decoding system, and the generated solution can be stored in a look-up table for subsequent implementation. However, the need for a look-up table has cost implications, and a method which obviates the need for a look-up table (or a large look-up table) would be preferable.
The first and second aspects of the invention have evolved from a realisation that certain mathematical constructive methods may be found for generating mappings between the address values and the intermediate node stimulation patterns and accordingly mappings between the intermediate nodes and the outputs, and that such constructive methods may be applied with specific choices of parameters to obtain specific configurations. Examples of such constructive methods which have been found include those based on affine geometries, projective geometries, concatenation and difference families. These constructive methods employ a plural-stage process, rather than a single-stage process which is used in obtaining a value or a set of values from a look-up table.
Accordingly, the method of the second aspect of the invention is characterised by the steps of: determining a plural-stage process to be performed by a decoder, said plural-stage process comprising at least a first stage in which results are determined and a second stage for which the results of the first stage are provided as inputs; arranging the decoder to perform the determined plural-stage process in determining which of the intermediate nodes to stimulate in response to each address value; and using the determined plural-stage process in said step of determining the group of the intermediate nodes to which the outputs are to be responsive.
Furthermore, the decoder system of the first aspect of the invention is characterised in that: the decoder is arranged to perform a plural-stage process in determining which of the intermediate nodes to stimulate in response to each address value, said plural-stage process comprising at least a first stage in which results are determined and a second stage for which the results of the first stage are provided as inputs.
As will be appreciated from the following description, it is therefore possible to employ relatively simple hard-wired circuitry or a computer performing a relatively simple programme, rather than using a single look-up table which, in the case of a display having several thousand electrodes, would be of considerable size.
In the context of this specification, the term xe2x80x9cplural-stage processxe2x80x9d is intended to include a process in which the result(s) of at least one first stage of the process is/are applied to at least one further stage of the process. For example, in one embodiment of the invention to be described in detail below: components of the process input are supplied to four pairs of first-stage elements (which may be look-up tables or logic arrays); the outputs of the first stage elements are supplied to four pairs of second-stage elements (which again may be look-up tables or logic arrays); the outputs of the second stage elements and components of the process input are applied to four pairs of third-stage elements (which again may be look-up tables or logic arrays); and the outputs of the third stage elements are applied to four 26-to-64 decoding devices in order to provide the decoder output. More generally, a plural-stage process includes a process performed by several layers of basic elements (such as look-up tables, gates and arithmetic elements) in which the output of at least one of the layers feeds into a subsequent layer. In another embodiment of the invention, corresponding stages of the process are performed by a programmed computer. In the context of this specification, the term xe2x80x9cplural-stage processxe2x80x9d does not include the processes performed by, for example, a simple logic gate (such as an AND or OR gate), a simple arithmetic unit (such as an adder or a multiplier), or a look-up table. Also, a plurality of processes which are performed independently of each other do not constitute a plural-stage process for the purposes of this specification.
Preferably, the system includes a resolution input for receiving a resolution signal representing any of a plurality of resolution values, and the decoder is responsive to the resolution signal such that: when the resolution signal has a first value, the combination of intermediate nodes stimulated in response to each address value causes a first number of the outputs to be stimulated, or to be stimulated beyond a predetermined threshold; and when the resolution signal has a second value, the combination of intermediate nodes stimulated in response to each address value causes a group of a second number of the outputs, greater than said first number, to be stimulated, or to be stimulated beyond the threshold.
Accordingly, in the case where the decoder system is used with a display, it is possible to stimulate a plurality of the display lines simultaneously, a property sometimes referred to later in this specification as xe2x80x9cmulti-line addressingxe2x80x9d. Moreover, it can be achieved that the stimulation applied to each of the desired display lines is above a certain threshold, whilst the stimulation applied to each of the remaining display lines is below a lower threshold.
Preferably, the decoder is responsive to the resolution signal such that when the resolution signal has at least one further value, the combination of intermediate nodes stimulated in response to each address value causes a, or a respective, group of a further number of the outputs to be stimulated, or to be stimulated beyond the threshold, the or each further different number being greater than the first number or the second number. In one advantageous approach, the further different number can be an integral multiple of the second number, in which case it is advantageous that each group, when the resolution signal has said one further value, is a union of a predetermined number of the groups when the resolution signal has said second value. An alternative is that the further different number is an integral multiple of the first number. Preferably, the arrangement is such that the outputs which are so stimulated in response to each address value when the resolution signal has said second value are physically grouped adjacent each other. Accordingly, in the case of a display, it is possible to stimulate blocks of lines of the display simultaneously, and the block stimulation may be hierarchically arranged.